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[VHDL-FPGA-Verilog] AlteraUSB

Description: Altera USB制作材料！有usb驱动！FPGA码源-Altera USB materials! There are usb drive! FPGA source code
Platform: | Size: 1750016 | Author: 杨寿佳 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] T2_USB_IN

Description: usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言-CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
Platform: | Size: 246784 | Author: ones | Hits:

[Other] CANBUS_USB_fpga

Description: 几个非常适用的用FPGA编写的实例，包含IIC。UART，USB等几个-Several very applicable to the preparation of examples of using FPGA, including IIC. UART, USB, etc.
Platform: | Size: 1516544 | Author: 云川 | Hits:

[Driver Develop] USB

Description: usb的驱动开发、应用开发（c/c++),以及其FPGA固件开发（VHDL）。-usb driver development, application development (c/c++), as well as its FPGA firmware development (VHDL).
Platform: | Size: 140288 | Author: zbs | Hits:

[VHDL-FPGA-Verilog] FPGAkaifashilidaohang

Description: 《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design -err
Platform: | Size: 1566720 | Author: 黑洞 | Hits:

[SCM] avrusb-20081126

Description: MEGA8做的USB下载线\avrusb-20081126-MEGA8 do USB download cable avrusb-20081126
Platform: | Size: 464896 | Author: 王飞 | Hits:

[Communication-Mobile] dataacquisitionwithFPGA

Description: 用fpga+usb显现的4通道800K的数据采集方案。-Fpga+ usb with emerging 4-channel data acquisition program of 800K.
Platform: | Size: 827392 | Author: lee | Hits:

[SCM] USB_kz

Description: 提供Cy7C68013 USB芯片开发源程序，由verilog编写-Cy7C68013 USB chip to provide the development of source code, prepared by the Verilog
Platform: | Size: 1024 | Author: sky | Hits:

[SCM] source_code

Description: 一些源程序，主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等-Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, such as radar target simulator
Platform: | Size: 6898688 | Author: 磊 | Hits:

[USB develop] USB2.0FPGAEXAMPLES

Description: 用于USB20芯片CY7C68013和FPGA之间的通信-comunication between USB and FPGA
Platform: | Size: 2853888 | Author: 熊小姐 | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[Embeded-SCM Develop] MYFX2

Description: usb cy7c68013开发板中CPLD的源代码-USB2.0-128P to restore the I2C settings dev_io
Platform: | Size: 2048 | Author: 桂霖 | Hits:

[Compress-Decompress algrithms] USB1C6

Description: 基于ALTERA CYCLONE 系列的一个USB实验例程-ALTERA CYCLONE series based on a USB experimental routines
Platform: | Size: 433152 | Author: xulinmeng | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Other] vhdl

Description: usb rtl code, to fpga or asic
Platform: | Size: 156672 | Author: andy | Hits:

[VHDL-FPGA-Verilog] USB-BLASTER

Description:
Platform: | Size: 2048 | Author: 李勇 | Hits:

[USB develop] ebook_USB2.0_intel_tranceiver

Description: High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
Platform: | Size: 342016 | Author: rex | Hits:

[VHDL-FPGA-Verilog] DE2_demonstrations

Description: DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等-DE2 development board information, mainly his example, contain a variety of interface program, such as VGA, USB, LCD, etc.
Platform: | Size: 44079104 | Author: 翁文天 | Hits:

[Com Port] usb_funct

Description: USB 2.0 verilog源代码,内包含详细文档资料。-USB 2.0 verilog source code, which contains detailed documentation.
Platform: | Size: 196608 | Author: 夏玥 | Hits:
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